ibmpc: Refactor code
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tmk
parent
4588ae8dac
commit
2f640de68d
1 changed files with 41 additions and 40 deletions
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@ -68,7 +68,7 @@ volatile uint8_t ibmpc_error = IBMPC_ERR_NONE;
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*/
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*/
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static volatile uint16_t recv_data = 0xFFFF;
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static volatile uint16_t recv_data = 0xFFFF;
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/* internal state of receiving data */
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/* internal state of receiving data */
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static volatile uint16_t isr_data = 0x8000;
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static volatile uint16_t isr_state = 0x8000;
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void ibmpc_host_init(void)
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void ibmpc_host_init(void)
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{
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{
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@ -194,7 +194,7 @@ int16_t ibmpc_host_recv_response(void)
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void ibmpc_host_isr_clear(void)
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void ibmpc_host_isr_clear(void)
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{
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{
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isr_data = 0x8000;
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isr_state = 0x8000;
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recv_data = 0xFFFF;
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recv_data = 0xFFFF;
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}
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}
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@ -205,50 +205,47 @@ ISR(IBMPC_INT_VECT)
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{
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{
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uint8_t dbit;
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uint8_t dbit;
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dbit = IBMPC_DATA_PIN&(1<<IBMPC_DATA_BIT);
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dbit = IBMPC_DATA_PIN&(1<<IBMPC_DATA_BIT);
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PINB|=0x01;
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isr_state = isr_state>>1;
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isr_data = isr_data>>1;
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if (dbit) isr_state |= 0x8000;
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if (dbit) isr_data |= 0x8000;
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// isr_data: state of receiving data from keyboard
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// isr_state: state of receiving data from keyboard
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// This is initialized with 0x8000 before start receiving data and MSB '1' of
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// the initial value is marker bit to discrimitate between protocols.
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// It stores sampled bit at MSB after right shift on each clock falling edge.
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//
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// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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// -----------------------------------------------------
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// -----------------------------------------------------
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// Initial: *1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 MSB sentinel
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// Initial: *1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 with MSB marker *1
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// XT IBM: b7 b6 b5 b4 b3 b2 b1 b0 | s1 s0 *1 0 0 0 0 0 after receiving **
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// XT_Type-1: b7 b6 b5 b4 b3 b2 b1 b0 | 1 0 *1 0 0 0 0 0 start bit 0 and 1 **
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// XT Clone: b7 b6 b5 b4 b3 b2 b1 b0 | s1 *1 0 0 0 0 0 0 after receiving
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// XT_Type-2: b7 b6 b5 b4 b3 b2 b1 b0 | 1 *1 0 0 0 0 0 0 start bit 1
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// AT: st pr b7 b6 b5 b4 b3 b2 | b1 b0 s0 *1 0 0 0 0 after receiving
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// AT: st pr b7 b6 b5 b4 b3 b2 | b1 b0 0 *1 0 0 0 0 start bit 0
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// AT**: pr b7 b6 b5 b4 b3 b2 b1 | b0 s0 *1 0 0 0 0 0 before stop bit **
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// AT**: pr b7 b6 b5 b4 b3 b2 b1 | b0 0 *1 0 0 0 0 0 before stop bit **
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//
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//
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// x x x x x x x x | 0 0 0 0 0 0 0 0 midway(0-7 bits received)
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// x x x x x x x x | 0 0 0 0 0 0 0 0 midway(0-7 bits received)
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// x x x x x x x x | 1 0 0 0 0 0 0 0 midway(8 bits received)
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// x x x x x x x x | *1 0 0 0 0 0 0 0 midway(8 bits received)
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// x x x x x x x x | 0 1 0 0 0 0 0 0 XT IBM-midway or AT-midway
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// x x x x x x x x | 0 *1 0 0 0 0 0 0 XT_Type1-midway or AT-midway
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// x x x x x x x x | 1 1 0 0 0 0 0 0 XT Clone-done
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// x x x x x x x x | 1 *1 0 0 0 0 0 0 XT_Type2-done
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// x x x x x x x x | 0 0 1 0 0 0 0 0 AT-midway
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// x x x x x x x x | 0 0 *1 0 0 0 0 0 AT-midway[b0=0]
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// x x x x x x x x | 1 0 1 0 0 0 0 0 XT IBM-done or AT-midway **
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// x x x x x x x x | 1 0 *1 0 0 0 0 0 XT_Type1-done or AT-midway[b0=1]
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// x x x x x x x x | x 1 1 0 0 0 0 0 illegal
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// x x x x x x x x | x 1 1 0 0 0 0 0 illegal
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// x x x x x x x x | x x 0 1 0 0 0 0 AT-done
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// x x x x x x x x | x x 0 1 0 0 0 0 AT-done
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// x x x x x x x x | x x 1 1 0 0 0 0 illegal
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// x x x x x x x x | x x 1 1 0 0 0 0 illegal
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// other states than avobe illegal
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// other states than above illegal
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//
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//
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// **: AT can take same as end sate of XT IBM(1010 000) when b0 is 1,
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// **: AT takes same state as XT_Type1-done(1010 000) in case that AT b0 is 1,
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// to discriminate between them we will have to wait a while for stop bit.
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// to discriminate between the two protocol we will have to wait a while for AT stop bit.
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//
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switch (isr_state & 0xFF) {
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// mask for isr_data:
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// 0x00A0(1010 0000) when XT IBM
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// 0x00C0(1100 0000) when XT Clone
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// 0x0010(xx01 0000) when AT
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//
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switch (isr_data & 0xFF) {
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case 0b00000000:
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case 0b00000000:
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case 0b10000000:
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case 0b10000000:
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case 0b01000000:
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case 0b01000000:
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case 0b00100000:
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case 0b00100000:
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// midway
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// midway
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return;
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goto NEXT;
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break;
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break;
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case 0b11000000:
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case 0b11000000:
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// XT Clone-done
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// XT_Type2-done
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recv_data = recv_data<<8;
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recv_data = recv_data<<8;
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recv_data |= (isr_data>>8) & 0xFF;
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recv_data |= (isr_state>>8) & 0xFF;
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goto DONE;
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goto DONE;
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break;
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break;
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case 0b10100000:
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case 0b10100000:
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@ -259,14 +256,12 @@ PINB|=0x01;
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while ( IBMPC_CLOCK_PIN&(1<<IBMPC_CLOCK_BIT) && us) { wait_us(1); us--; }
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while ( IBMPC_CLOCK_PIN&(1<<IBMPC_CLOCK_BIT) && us) { wait_us(1); us--; }
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if (us) {
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if (us) {
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// found stop bit: return immediately and process the stop bit in ISR
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// found stop bit: AT-midway - process the stop bit in next ISR
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// AT-midway
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goto NEXT;
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return;
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} else {
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} else {
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// no stop bit
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// no stop bit: XT_Type1-done
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// XT-IBM-done
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recv_data = recv_data<<8;
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recv_data = recv_data<<8;
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recv_data |= (isr_data>>8) & 0xFF;
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recv_data |= (isr_state>>8) & 0xFF;
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goto DONE;
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goto DONE;
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}
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}
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}
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}
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@ -277,7 +272,7 @@ PINB|=0x01;
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case 0b11010000:
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case 0b11010000:
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// AT-done
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// AT-done
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recv_data = recv_data<<8;
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recv_data = recv_data<<8;
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recv_data |= (isr_data>>6) & 0xFF;
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recv_data |= (isr_state>>6) & 0xFF;
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goto DONE;
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goto DONE;
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break;
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break;
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case 0b01100000:
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case 0b01100000:
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@ -287,14 +282,20 @@ PINB|=0x01;
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case 0b01110000:
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case 0b01110000:
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case 0b11110000:
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case 0b11110000:
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default: // xxxx_oooo(any 1 in low nibble)
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default: // xxxx_oooo(any 1 in low nibble)
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recv_data = isr_data;
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// Illegal
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goto ERROR;
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break;
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break;
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}
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}
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ERROR:
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isr_state = 0x8000;
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recv_data = 0xFF00; // clear data and scancode of error 0x00
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ibmpc_error = 0xFF;
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return;
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DONE:
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DONE:
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// TODO: check protocol change to support keyboard howswap
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// not correct if there is clock edge within short time like 100us after receving data
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// TODO: process error code: 0x00(AT), 0xFF(XT) in particular
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// TODO: process error code: 0x00(AT), 0xFF(XT) in particular
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isr_data = 0x8000; // clear to next data
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isr_state = 0x8000; // clear to next data
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NEXT:
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return;
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return;
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}
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}
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