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archimedes: Fix serial timing

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tmk 2023-10-20 00:15:40 +09:00
parent 643cee3280
commit 909b37d641
2 changed files with 12 additions and 6 deletions
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5
converter/archimedes_usb/config.h
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@ -46,12 +46,15 @@ SOFTWARE.
* asynchronous, negative logic, 31250 baud
* start bit(0), 8-bit data(LSB first), stop bit(1)
*/
#define SERIAL_SOFT_DEBUG
#define SERIAL_SOFT_BAUD 31250
#define SERIAL_SOFT_PARITY_NONE
#define SERIAL_SOFT_BIT_ORDER_LSB
#define SERIAL_SOFT_LOGIC_NEGATIVE
/* debug for signal timing, see debug pin with oscilloscope */
#define SERIAL_SOFT_DEBUG_INIT() (DDRD |= 1<<2)
#define SERIAL_SOFT_DEBUG_TGL() (PIND |= 1<<2)
/* RXD Port */
#define SERIAL_SOFT_RXD_ENABLE
#define SERIAL_SOFT_RXD_DDR DDRD