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ibmpc_usb: Fix hard reset code

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This commit is contained in:
tmk 2020-01-23 23:40:04 +09:00
parent c2e8c0d43e
commit a42cc4bddb
3 changed files with 24 additions and 13 deletions
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19
converter/ibmpc_usb/config.h
View file

@ -44,32 +44,39 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
* Pin and interrupt configuration
*/
#if defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U2__) || defined(__AVR_AT90USB1286__)
/* uses INT1 for clock line */
/* clock line */
#define IBMPC_CLOCK_PORT PORTD
#define IBMPC_CLOCK_PIN PIND
#define IBMPC_CLOCK_DDR DDRD
#define IBMPC_CLOCK_BIT 1
/* data line */
#define IBMPC_DATA_PORT PORTD
#define IBMPC_DATA_PIN PIND
#define IBMPC_DATA_DDR DDRD
#define IBMPC_DATA_BIT 0
/* reset line */
#define IBMPC_RST_PORT PORTB
#define IBMPC_RST_PIN PINB
#define IBMPC_RST_DDR DDRB
#define IBMPC_RST_BIT1 6
#define IBMPC_RST_BIT2 7
/* reset for XT keyboard: low pulse for 500ms and after that HiZ for safety */
#define IBMPC_RESET() do { \
/* reset for XT Type-1 keyboard: low pulse for 500ms */
#define IBMPC_RST_HIZ() do { \
IBMPC_RST_PORT &= ~(1<<IBMPC_RST_BIT1); \
IBMPC_RST_DDR &= ~(1<<IBMPC_RST_BIT1); \
IBMPC_RST_PORT &= ~(1<<IBMPC_RST_BIT2); \
IBMPC_RST_DDR &= ~(1<<IBMPC_RST_BIT2); \
} while (0)
#define IBMPC_RST_LO() do { \
IBMPC_RST_PORT &= ~(1<<IBMPC_RST_BIT1); \
IBMPC_RST_DDR |= (1<<IBMPC_RST_BIT1); \
IBMPC_RST_PORT &= ~(1<<IBMPC_RST_BIT2); \
IBMPC_RST_DDR |= (1<<IBMPC_RST_BIT2); \
_delay_ms(500); \
IBMPC_RST_DDR &= ~(1<<IBMPC_RST_BIT1); \
IBMPC_RST_DDR &= ~(1<<IBMPC_RST_BIT2); \
} while (0)
/* interrupt for clock line */
#define IBMPC_INT_INIT() do { \
EICRA |= ((1<<ISC11) | \
(0<<ISC10)); \

11
converter/ibmpc_usb/ibmpc_usb.c
View file

@ -77,10 +77,15 @@ DONE:
return id;
}
void hook_early_init(void)
{
ibmpc_host_init();
ibmpc_host_enable();
}
void matrix_init(void)
{
debug_enable = true;
ibmpc_host_init();
// initialize matrix state: all keys off
for (uint8_t i=0; i < MATRIX_ROWS; i++) matrix[i] = 0x00;
@ -146,7 +151,9 @@ uint8_t matrix_scan(void)
// XT: hard reset 500ms for IBM XT Type-1 keyboard and clones
// XT: soft reset 20ms min(clock Lo)
ibmpc_host_disable(); // soft reset: inihibit(clock Lo/Data Hi)
IBMPC_RESET(); // hard reset
IBMPC_RST_LO();
wait_ms(500);
IBMPC_RST_HIZ();
ibmpc_host_enable(); // soft reset: idle(clock Hi/Data Hi)
// TODO: should in while disabling interrupt?

7
tmk_core/protocol/ibmpc.c
View file

@ -71,11 +71,8 @@ volatile uint8_t ibmpc_error = IBMPC_ERR_NONE;
void ibmpc_host_init(void)
{
// initialize reset pin
IBMPC_RST_PORT |= (1<<IBMPC_RST_BIT1);
IBMPC_RST_DDR |= (1<<IBMPC_RST_BIT1);
IBMPC_RST_PORT |= (1<<IBMPC_RST_BIT2);
IBMPC_RST_DDR |= (1<<IBMPC_RST_BIT2);
// initialize reset pin to HiZ
IBMPC_RST_HIZ();
inhibit();
IBMPC_INT_INIT();
IBMPC_INT_OFF();