2016-03-01 21:37:22 -08:00
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#ifndef XT_IO_H
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#define XT_IO_H
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2018-03-02 13:56:46 +09:00
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#define XT_DATA_IN() do { \
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XT_DATA_DDR &= ~(1<<XT_DATA_BIT); \
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XT_DATA_PORT |= (1<<XT_DATA_BIT); \
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} while (0)
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2016-03-01 21:37:22 -08:00
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2018-03-02 13:56:46 +09:00
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#define XT_DATA_READ() (XT_DATA_PIN&(1<<XT_DATA_BIT))
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#define XT_DATA_LO() do { \
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XT_DATA_PORT &= ~(1<<XT_DATA_BIT); \
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XT_DATA_DDR |= (1<<XT_DATA_BIT); \
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} while (0)
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#define XT_CLOCK_IN() do { \
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XT_CLOCK_DDR &= ~(1<<XT_CLOCK_BIT); \
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XT_CLOCK_PORT |= (1<<XT_CLOCK_BIT); \
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} while (0)
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#define XT_CLOCK_READ() (XT_CLOCK_PIN&(1<<XT_CLOCK_BIT))
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#define XT_CLOCK_LO() do { \
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XT_CLOCK_PORT &= ~(1<<XT_CLOCK_BIT); \
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XT_CLOCK_DDR |= (1<<XT_CLOCK_BIT); \
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} while (0)
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2018-02-28 15:48:06 +09:00
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2016-03-01 21:37:22 -08:00
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#endif
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